Few works in FPGA

All has been writen with a MachXO3-9400 Development Board

datasheet accessible

• SWITCH.vhdl - Connecting a simple button in vhdl
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; ------------------------------------------------------------------------------- -- Latch switch to turn on/off led -- NSWITCH : in - switchs on board / general purpose -- NLED : out - leds on board -- CLK : out - intern clock of fpga ------------------------------------------------------------------------------- library machXO3; use machXO3.all; entity S_R_latch_top is port (button : in std_logic_vector(5 downto 2); led : out std_logic_vector(8 downto 1); CLK_OUT : out std_logic); end S_R_latch_top; architecture Behavioral of S_R_latch_top is signal flipflop : std_logic_vector(1 downto 0); signal osc_int : std_logic; component OSCH -- synthesis translate_off generic (NOM_FREQ : string := "2.56"); -- synthesis translate_on port (STDBY : in std_logic; OSC : out std_logic; SEDSTDBY : out std_logic); end component OSCH; attribute NOM_FREQ : string; attribute NOM_FREQ of OSCinst0 : label is "2.56"; begin OSCInst0 : OSCH -- synthesis translate_off generic map(NOM_FREQ => "2.56") -- synthesis translate_on port map (STDBY => '0', OSC => osc_int, SEDSTDBY => open ); led_toggle_proc : process(osc_int) begin if rising_edge(osc_int) then if rising_edge(button(2)) then led(1) <= '1'; end if; if falling_edge(button(2)) then led(1) <= '1'; end if; end if; end process led_toggle_proc; CLK_OUT <= osc_int; end Behavioral;
• MUX81.vhdl - Making a simple led logic function
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library machXO3; use machXO3.all; ------------------------------------------------------------------------------- -- Mux 8:1 with SAS method (behavior style) ------------------------------------------------------------------------------- entity mux81 is port (Data_in : in std_logic_vector(7 downto 0); SEL : in std_logic_vector(2 downto 0); F_CTRL : out std_logic); end mux81; architecture behave_mux81 of mux81 is begin process(Data_in, SEL) begin if ( SEL = "111") then F_CTRL <= Data_in(7); elsif ( SEL = "110") then F_CTRL <= Data_in(6); elsif ( SEL = "101") then F_CTRL <= Data_in(5); elsif ( SEL = "100") then F_CTRL <= Data_in(4); elsif ( SEL = "011") then F_CTRL <= Data_in(3); elsif ( SEL = "010") then F_CTRL <= Data_in(2); elsif ( SEL = "001") then F_CTRL <= Data_in(1); elsif ( SEL = "000") then F_CTRL <= Data_in(0); else F_CTRL = '0'; end if; end process; end behave_mux81;
• DEBOUNCE.vhdl - Debouncing a button
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library machXO3; use machXO3.all; ------------------------------------------------------------------------------- -- Debouncer for a led toggle switch ------------------------------------------------------------------------------- entity toggle_sw is port ( SW : in std_logic; led : out std_logic; CLK_OUT : out std_logic; SW_up, SW_down : inout std_logic ); end toggle_sw; architecture rtl of toggle_sw is signal clk20 : std_logic; signal sw_i : std_logic; signal sw_sreg : std_logic_vector(3 downto 0) := x"0"; signal counter : unsigned(15 downto 0); signal led_sig : std_logic; signal led_i : std_logic := '0'; signal sw_inv_sync : std_logic; signal sw_sync : std_logic; component OSCH -- synthesis translate_off generic (NOM_FREQ : string := "20.46"); -- synthesis translate_on port ( STDBY : in std_logic; OSC : out std_logic; SEDSTDBY : out std_logic ); end component; attribute NOM_FREQ : string; attribute NOM_FREQ of OSCinst0 : label is "20.46"; begin OSCInst0 : OSCH -- synthesis translate_off generic map(NOM_FREQ => "20.46") -- synthesis translate_on port map ( STDBY => '0', OSC => clk20, SEDSTDBY => open ); sw_i <= not SW; sync : process(clk20) begin if rising_edge(clk20) then --sw_sreg <= sw_sreg(2 downto 0) & sw_i; sw_sreg(3 downto 1) <= sw_sreg(2 downto 0); sw_sreg(0) <= sw_i; end if; end process sync; edge_detection : process(clk20) begin if rising_edge(clk20) then --rising edge -- if sw_sreg = "0111" then -- led_i <= not led_i; -- end if; --rfalling edge if sw_sreg = "1000" then led_i <= not led_i; end if; end if; end process; -- sync : process(SW) -- begin -- if rising_edge(SW) then -- led_i <= not led_i; -- end if; -- end process sync; led <= led_i; SW_up <= sw_sreg(0); SW_down <= led_i; -- debounce : process(clk20) -- begin -- if (rising_edge(clk20)) then -- if (sw_sync = '0') then -- counter <= "0000000000000000"; -- end if; -- -- if (sw_sync = '1') then -- counter <= counter + 1; --end if; -- -- if (counter = "1111111111111111") then -- SW_down <= '1'; -- SW_up <= ; --end if; --end if; --end process debounce; -- toggle : process(SW_down) -- begin -- if (SW_down = '1') then -- led_sig <= not led_sig; -- -- elsif (SW_down = '1' and led_sig = '1') then -- -- led_sig <= not led_sig; -- end if; -- end process toggle; --led <= not led_sig; CLK_OUT <= clk20; end rtl;
• MOORE.vhdl - Coding a moore machine
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library machXO3; use machXO3.all; ------------------------------------------------------------------------------- -- Moore machine -- 1 input : the switch -- outputs : leds (8) ------------------------------------------------------------------------------ -- idea : for each push on the switch, the leds count one in binary -- example : *push* led vector is now "00000001", again : "00000010" usw... ------------------------------------------------------------------------------- entity moore is port ( SW : in std_logic; leds : out std_logic_vector(8 downto 1) clk_out : out std_logic ); end moore;
• MOTOR.vhdl - Code for a 3D-printer rotating motor
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library machXO3; use machXO3.all; ------------------------------------------------------------------------------- -- switch step motor IO connect. ------------------------------------------------------------------------------- entity motor is port ( D : out std_logic_vector(4 downto 1); CLK_OUT : out std_logic ); end motor; architecture behave of motor is signal clkcount : signed (6 downto 0); signal clktik : std_logic; signal pulsecount : signed (11 downto 0); signal sel : std_logic_vector(2 downto 0); component OSCH -- synthesis translate_off generic (NOM_FREQ : string := "20.46"); -- synthesis translate_on port ( STDBY : in std_logic; OSC : out std_logic; SEDSTDBY : out std_logic ); end component; attribute NOM_FREQ : string; attribute NOM_FREQ of OSCinst0 : label is "20.46"; begin OSCInst0 : OSCH -- synthesis translate_off generic map(NOM_FREQ => "20.46") -- synthesis translate_on port map ( STDBY => '0', OSC => clk20, SEDSTDBY => open ); --Pulse generator tiktak : process (clk20) variable clkdiv : integer := 80; -- clk=20 MHz => T=48ns so 4µs for each variable max : integer := 255; -- tik makes 80 couting of clk begin if rising_edge(clk20) then if clkcount = clkdiv then clkcount <= 0; pulsecount <= pulsecount + 1; -- pulsecount can be fill in 2**12 x 4 -- µs = 16ms so 1 pulse each 16ms else clkcount <= clkcount + 1; end if; if pulsecount = max then sel <= sel + 1; end if; end if; case sel is when "100" => D <= "1000"; when "011" => D <= "0100"; when "010" => D <= "0010"; when "001" => D <= "0001"; when "000" => D <= "0000"; when others => D <= "0000"; end case; end process tiktak; CLK_OUT <= clk20; end behave;
• AMPEL.vhdl - Coding a light trafic
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library machXO3; use machXO3.all; ------------------------------------------------------------------------------- -- Ampel red. -- *push* wait 3s led1 3s led2 3s led3 ------------------------------------------------------------------------------- entity traffic_light_controller is port (sensor : in std_logic; -- Sensor -- clock rst_n : in std_logic; -- reset active low light_highway : out std_logic_vector(2 downto 0); -- light outputs of high way light_farm : out std_logic_vector(2 downto 0) -- light -- outputs of -- farm way --RED_YELLOW_GREEN ); end traffic_light_controller; -- Traffic ligh system for a intersection between highway and farm way -- There is a sensor on the farm way side, when there are vehicles, -- Traffic light turns to YELLOW, then GREEN to let the vehicles cross the -- highway -- Otherwise, always green light on Highway and Red light on farm way architecture traffic_light of traffic_light_controller is signal clk20 : std_logic; signal sw_i : std_logic; signal sw_sreg : std_logic_vector(3 downto 0) := x"0"; signal sw_sync : std_logic; signal led_i : std_logic_vector(3 downto 1) := "000"; signal sel : unsigned(1 downto 0) := "00"; signal trigger : std_logic; signal cnt : unsigned(27 downto 0) := "0000000000000000000000000000"; signal trig_cnt : unsigned(27 downto 0) := "0000000000000000000000000000"; component OSCH -- synthesis translate_off generic (NOM_FREQ : string := "20.46"); -- synthesis translate_on port ( STDBY : in std_logic; OSC : out std_logic; SEDSTDBY : out std_logic ); end component; attribute NOM_FREQ : string; attribute NOM_FREQ of OSCinst0 : label is "20.46"; signal counter_1s : std_logic_vector(27 downto 0) := x"0000000"; signal delay_count : std_logic_vector(3 downto 0) := x"0"; signal delay_10s, delay_3s_F, delay_3s_H, RED_LIGHT_ENABLE, YELLOW_LIGHT1_ENABLE, YELLOW_LIGHT2_ENABLE : std_logic := '0'; signal clk_1s_enable : std_logic; -- 1s clock enable type FSM_States is (HGRE_FRED, HYEL_FRED, HRED_FGRE, HRED_FYEL); -- HGRE_FRED : Highway green and farm red -- HYEL_FRED : Highway yellow and farm red -- HRED_FGRE : Highway red and farm green -- HRED_FYEL : Highway red and farm yellow signal current_state, next_state : FSM_States; begin OSCInst0 : OSCH -- synthesis translate_off generic map(NOM_FREQ => "20.46") -- synthesis translate_on port map ( STDBY => '0', OSC => clk20, SEDSTDBY => open ); sw_i <= not SW; sync : process(clk20) begin if rising_edge(clk20) then --sw_sreg <= sw_sreg(2 downto 0) & sw_i; sw_sreg(3 downto 1) <= sw_sreg(2 downto 0); sw_sreg(0) <= sw_i; end if; end process sync; -- edge_detection : process(clk20) -- begin -- if rising_edge(clk20) then -- if sw_sreg = "1000" then -- sel <= sel + 1; -- end if; -- end if; -- end process edge_detection; -- next state FSM sequential logic process(clk, rst_n) begin if(rst_n = '0') then current_state <= HGRE_FRED; elsif(rising_edge(clk20)) then current_state <= next_state; end if; end process; -- FSM combinational logic process(current_state, sensor, delay_3s_F, delay_3s_H, delay_10s) begin case current_state is when HGRE_FRED => -- When Green light on Highway and Red -- light on Farm way RED_LIGHT_ENABLE <= '0'; -- disable RED light delay counting YELLOW_LIGHT1_ENABLE <= '0'; -- disable YELLOW light -- Highway delay counting YELLOW_LIGHT2_ENABLE <= '0'; -- disable YELLOW light -- Farmway delay counting light_highway <= "001"; -- Green light on Highway light_farm <= "100"; -- Red light on Farm way if(sensor = '1') then -- if -- vehicle is detected on farm way -- by sensors next_state <= HYEL_FRED; -- High way turns to Yellow else next_state <= HGRE_FRED; -- Otherwise, remains GREEN ON highway and RED -- on Farm way end if; when HYEL_FRED => -- When Yellow light on Highway and Red -- light on Farm way light_highway <= "010"; -- Yellow light on Highway light_farm <= "100"; -- Red light on Farm way RED_LIGHT_ENABLE <= '0'; -- disable -- RED light delay counting YELLOW_LIGHT1_ENABLE <= '1'; -- enable YELLOW light Highway -- delay counting YELLOW_LIGHT2_ENABLE <= '0'; -- disable YELLOW light Farmway -- delay counting if(delay_3s_H = '1') then -- if Yellow light delay counts to 3s, -- turn Highway to RED, -- Farm way to green light next_state <= HRED_FGRE; else next_state <= HYEL_FRED; -- -- Remains Yellow on highway and Red on Farm -- way -- -- if Yellow light not yet in 3s end if; when HRED_FGRE => light_highway <= "100"; -- RED light on Highway -- light_farm <= "001";-- GREEN -- light on Farm way -- RED_LIGHT_ENABLE <= '1';-- -- enable RED light delay counting YELLOW_LIGHT1_ENABLE <= '0'; -- disable YELLOW light -- Highway delay counting YELLOW_LIGHT2_ENABLE <= '0'; -- disable YELLOW light -- Farmway delay counting if(delay_10s = '1') then -- if RED light on highway is 10s, Farm way turns to Yellow next_state <= HRED_FYEL; else next_state <= HRED_FGRE; -- Remains if delay counts for RED light on highway -- not enough 10s end if; when HRED_FYEL => light_highway <= "100"; -- RED light on Highway light_farm <= "010"; -- Yellow light on Farm way -- RED_LIGHT_ENABLE <= '0'; -- -- disable RED light delay -- counting YELLOW_LIGHT1_ENABLE <= '0'; -- disable YELLOW light -- Highway delay counting YELLOW_LIGHT2_ENABLE <= '1'; -- enable YELLOW light -- Farmway delay counting if(delay_3s_F = '1') then -- if delay for Yellow light is 3s, -- turn highway to GREEN light -- Farm way to RED Light next_state <= HGRE_FRED; else next_state <= HRED_FYEL; -- if not enough 3s, remain the same state end if; when others => next_state <= HGRE_FRED; -- Green on -- highway, -- red on -- farm way end case; end process; -- Delay counts for Yellow and RED light process(clk20) begin if(rising_edge(clk20)) then if(clk_1s_enable = '1') then if(RED_LIGHT_ENABLE = '1' or YELLOW_LIGHT1_ENABLE = '1' or YELLOW_LIGHT2_ENABLE = '1') then delay_count <= delay_count + x"1"; if((delay_count = x"9") and RED_LIGHT_ENABLE = '1') then delay_10s <= '1'; delay_3s_H <= '0'; delay_3s_F <= '0'; delay_count <= x"0"; elsif((delay_count = x"2") and YELLOW_LIGHT1_ENABLE = '1') then delay_10s <= '0'; delay_3s_H <= '1'; delay_3s_F <= '0'; delay_count <= x"0"; elsif((delay_count = x"2") and YELLOW_LIGHT2_ENABLE = '1') then delay_10s <= '0'; delay_3s_H <= '0'; delay_3s_F <= '1'; delay_count <= x"0"; else delay_10s <= '0'; delay_3s_H <= '0'; delay_3s_F <= '0'; end if; end if; end if; end if; end process; -- create delay 1s process(clk) begin if(rising_edge(clk20)) then counter_1s <= counter_1s + x"0000001"; if(counter_1s >= x"0000003") then -- x"0004" is -- for simulation -- change to x"2FAF080" for 50 MHz clock -- running real FPGA counter_1s <= x"0000000"; end if; end if; end process; clk_1s_enable <= '1' when counter_1s = x"0003" else '0'; -- x"0002" is for simulation -- x"2FAF080" for 50Mhz clock on FPGA end traffic_light;
• SYNTH.vhdl - Coding a sequencer synth
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library machXO3; use machXO3.all; ------------------------------------------------------------------------------- -- beep machine. bip bop bip ------------------------------------------------------------------------------- entity bip is port ( do4 : in std_logic; si3 : in std_logic; la3 : in std_logic; sol3 : in std_logic; clk_out : out std_logic; clk_test : out std_logic; pwm_out : out std_logic ); end bip; architecture bipbop of bip is signal clk1kHz : std_logic; signal counter_clk : unsigned(11 downto 0); signal pwm_counter : unsigned(11 downto 0); signal pwm_threshold : unsigned(11 downto 0); signal pwm_out_int : std_logic := '0'; signal button_do4 : std_logic; signal button_si3 : std_logic; signal button_la3 : std_logic; signal button_sol3 : std_logic; signal sw_sreg : std_logic_vector(3 downto 0) := x"0"; signal clk2 : std_logic; signal clk_divided : std_logic; -- Horloge divis�e signal counter_1kHz : integer range 0 to 1039 := 0; constant divider_value : integer := 104; -- Divise par 2.08MHz par 104 pour obtenir 10 kHz puis bas� sur PWM signal pwm_start : std_logic; component OSCH -- synthesis translate_off generic (NOM_FREQ : string := "2.08"); -- synthesis translate_on port ( STDBY : in std_logic; OSC : out std_logic; SEDSTDBY : out std_logic ); end component; attribute NOM_FREQ : string; attribute NOM_FREQ of OSCinst0 : label is "2.08"; begin OSCInst0 : OSCH -- synthesis translate_off generic map(NOM_FREQ => "2.08") -- synthesis translate_on port map ( STDBY => '0', OSC => clk2, SEDSTDBY => open ); -- Instanciation du module de debouncing pour le bouton Do4 button_do4 <= not do4; button_si3 <= not si3; button_la3 <= not la3; button_sol3 <= not sol3; sync : process(clk2) begin if rising_edge(clk2) then sw_sreg(3 downto 1) <= sw_sreg(2 downto 0); sw_sreg(0) <= button_do4; sw_sreg(3 downto 1) <= sw_sreg(2 downto 0); sw_sreg(0) <= button_si3; sw_sreg(3 downto 1) <= sw_sreg(2 downto 0); sw_sreg(0) <= button_la3; sw_sreg(3 downto 1) <= sw_sreg(2 downto 0); sw_sreg(0) <= button_sol3; end if; end process sync; process(clk2) begin if rising_edge(clk2) then -- Division de l'horloge clk2 pour obtenir clk1kHz_divided if counter_1kHz = divider_value then counter_1kHz <= 0; clk_divided <= not clk_divided; else counter_1kHz <= counter_1kHz + 1; end if; end if; end process; -- Configuration des seuils de la PWM pour chaque note -- 208 kHz / Note_voulue = int � donner au code process(clk_divided) begin if rising_edge(clk_divided) then if button_do4 = '1' then -- Bouton enfonc�, d�marrer la PWM pwm_start <= '1'; if pwm_counter = 0 then pwm_out_int <= not pwm_out_int; pwm_counter <= to_unsigned(38, pwm_counter'length); -- DO4 Conversion explicite -- 10 kHz / 262 Hz = 38 else pwm_out_int <= '0'; pwm_counter <= pwm_counter - 1; end if; elsif button_si3 = '1' then -- Bouton enfonc�, d�marrer la PWM pwm_start <= '1'; if pwm_counter = 0 then pwm_out_int <= not pwm_out_int; pwm_counter <= to_unsigned(40, pwm_counter'length); -- SI3 Conversion explicite -- 10 kHz / 247 Hz = 40 else pwm_out_int <= '0'; pwm_counter <= pwm_counter - 1; end if; elsif button_la3 = '1' then -- Bouton enfonc�, d�marrer la PWM pwm_start <= '1'; if pwm_counter = 0 then pwm_out_int <= not pwm_out_int; pwm_counter <= to_unsigned(45, pwm_counter'length); -- LA3 Conversion explicite -- 10 kHz / 220 Hz = 45 else pwm_out_int <= '0'; pwm_counter <= pwm_counter - 1; end if; elsif button_sol3 = '1' then -- Bouton enfonc�, d�marrer la PWM pwm_start <= '1'; if pwm_counter = 0 then pwm_out_int <= not pwm_out_int; pwm_counter <= to_unsigned(51, pwm_counter'length); -- SOL3 Conversion explicite -- 10 kHz / 196 Hz = 51 else pwm_out_int <= '0'; pwm_counter <= pwm_counter - 1; end if; else -- Bouton rel�ch�, arr�ter la PWM pwm_start <= '0'; pwm_out_int <= '0'; pwm_counter <= (others => '0'); end if; end if; end process; -- Assignation des signaux de sortie pwm_out <= pwm_out_int; clk_out <= clk_divided; clk_test <= clk2; end bipbop;